In more modern all points addressable (APA) raster display designs, an image to be viewed is stored point by point in a memory subsystem, a frame buffer, comprising dynamic random access memory arrays. This design approach allows independent updating of every pixel so that arbitrarily complex images can be produced. While this design approach allows greater display flexibility, it also gives rise to the requirement of higher display performance because of the larger number of image bits to be displayed.
Within the frame buffer, generally there are two primary processes at work, one for updating the frame buffer to change the image it represents, and another for refreshing the video monitor. Both processes tend to place a challenging requirement on the available bandwidth of the frame buffer. As frame buffer sizes grow because of both decreasing memory costs and increasing image complexity and resolutions in certain applications, the bandwidth requirements also increase proportionally.
Early displays employed magnetic disks and drum for the storage of images because of the prohibitive high cost of semiconductor memory. Later, when semiconductor memory becomes more economical, some display design used large scale integration shift registers. Since both the magnetic and the shift register types of memory are relative slow speed, displays employing these types of memory tend to have relatively low resolution and/or low performance. It was not until more recently that integrated circuit random access memory arrays have become sufficiently low cost enough to be incorporated in APA raster scan displays.
Conventional integrated circuit RAM architectures are heretofore well known. For instance, U.S. Pat. No. 3,387,286 entitled "Field Effect Transistor Memory", issued to R. H. Dennard and assigned to the common assignee of the present application discloses a RAM architecture wherein memory cells are arranged in an array having each memory cell coupled to at least one of a plurality of word lines for the memory and at least one of a plurality of bit lines for the memory. According to the Dennard patent, one memory cell in the array can be accessed at any one cycle for a read or write operation.
Some earlier integrated circuit RAM feature simultaneous erasure. For instance, U.S. Pat. No. 4,172,291, entitled "Preset Circuit For Information Storage Devices", and issued to W. K. Owens, et al, discloses an electronic circuit for simultaneous erasure of all the information stored in an electronic information storage device and enter a predetermined new pattern of information. The patent teaches a bipolar static memory array with an additional transistor current-conducting circuit included on a predetermined side of each memory cell. The additional transistor current conducting circuit in the memory cells along each row are coupled to an an additional word line which is connected to a current switch for the row. An appropriate signal activates the current switch to switch row current temporarily to the additional word line thereby erasing the old data and enter the predetermined pattern of information in the storage device.
Another prior integrated circuit RAM featuring erasure of a number of bits at a time is described in U.S. Pat. No. 4,099,069, entitled "Circuit Producing A Common Clear Signal For Erasing Selected Arrays In A MNOS Memory System" and issued to J. R. Cricchi, et al. According to the patent, memory transistors are arranged in blocks in one of two islands. Erasure of the data stored in a selected block is accomplished by coupling the gates of all the memory transistors to a first voltage and applying a second voltage to the substrate of the memory transistors in the selected block. The first and second voltages are generated by a logic circuit contained substantially in the second island.
Heretofore, some commercial integrated circuit RAM architecture also feature an improved mode of writing a multiple number of memory cells. For instance, as an example of such commercially available RAM, the TMS 4164 64K RAM by Texas Instruments features a page-mode operation for faster access (Texas Instruments July 1980 Catalog, revised May 1982, pp 40-53). With the featured page mode, a multiple number of bits constituting a page can be read/written from or onto the memory array. Page-mode operation allows effectively faster memory access by keeping the same row address and strobing successive column addresses. The access speed improvement of about 30%-50% is possible because the time required to setup and strobe sequential row addresses of the same page is eliminated. Such a page-mode operation is useful for speeding up the reset of APA display frame buffers.
A frequent bottleneck in the design of such APA raster scan displays is the limited available bandwidth of the memory subsystem, more specifically, the frame buffer.